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The first system-on-chip (SoC) developed by the Finnish SoC Hub consortium has been registered. Project partners will then focus on improving SoC design, automation, and performance. The first of three chips developed by the consortium will be ready for deployment in early 2022.

The SoC Hub initiative, coordinated by the University of Tampere, Finland, and Nokia, was launched last year. The co-creation activities carried out by the partners go far beyond the framework of a conventional research project. Finland’s SoC Hub said it set out to develop the field of SoC design as a pioneer in Europe and improve Finland’s competitive position.

“The SoC was developed using the same methods used in industrial production, such as designing for testability, thorough verification, and focusing on system-level integration instead of single modules,” says Ari. Kulmala, Professor of SoC Design Practice at the University of Tampere.

According to Kulmala, the chip can also be tested by external stakeholders as it includes a development kit, and it can be integrated into a wide range of other systems.

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One of the main goals of the SoC Hub project is to enable the rapid prototyping of new ideas, for example in the Internet of Things (IoT), machine learning and 5G and 6G technologies on silicon.

The newly registered Ballast chip is the first in a series of three chips. The chip will be made by TSMC, a semiconductor chip maker, the SoC Hub said.

The chip is fabricated using TSMC’s ultra-low leakage 22nm process, which is particularly well suited for IoT and Edge devices. Ballast contains several different RISC-V processor cores, a digital signal processor, an AI accelerator, rich sensor-like interfaces, and an expansion interface to FPGA. A full software stack – including drivers, software development tools, and chip debugging support – has also been implemented. The chip supports real-time and Linux operating systems simultaneously, the SoC Hub says.

“It was a pleasure to work with the SoC Hub team. They were extremely quick to develop the chip and the quality of work was top notch,” says imec.IC-link, imec Member, Director of Development commercial Lower Dorren.

Given its large size, the chip was created in a very short time, according to the SoC Hub.

“A lot of work has been done to allow harmonious collaboration between the University and the partner companies. Several early-career researchers were involved in the design of Ballast and therefore had the opportunity to apply the knowledge acquired during their studies in an industrial project”, explains Timo Hämäläinen, director of the computer science unit at the University of Tampere.

Besides the development of the SoC, the first phase of the project was also a major undertaking, involving the constitution of the consortium and the preparation of the necessary software and license agreements. Led by Tampere University and Nokia, the consortium includes CoreHW, VLSI Solution, Siru Innovations, TTTEch Flexibilis, Procemex, Wapice and Cargotec as partners, the SoC Hub said.

In the project, funded by Business Finland, three SoCs will be registered by the end of 2023. Use cases for the chips will be planned with the project consortium.

“In the next phases of the project, we will be able to focus even more on the systematics, automation and performance of the SoCs. Although we have achieved our first goal, we are still moving forward immediately. SoC development is now, not tomorrow,” Hämäläinen points out.

This first appeared in the CommsWire subscription newsletter on December 14, 2021.

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